Design and optimization of DSP architectures for multi-context FPGA with dynamic reconfiguration
Field Programmable Gate Arrays (FPGAs) are now widely adopted as hardware accelerators due to their inherent parallel processing capability. However, the sub-optimal logic utilization and large reconfiguration latency in conventional single-context FPGAs pose constraints on their usage for applicat...
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| Format: | Thesis |
| Language: | English |
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2016
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| Online Access: | https://hdl.handle.net/10356/69398 |