High speed ADC
This report presents a simulation model design of a 10-bits pipelined ADC with background calibration. The proposed architecture includes a 3-bit ADC, five 1.5-bits ADC and a 2-bit ADC in a cascade. Some non-ideal errors and offsets are introduced in the pipelined ADC during simulation to model the...
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| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2017
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| Online Access: | http://hdl.handle.net/10356/71830 |