| Summary: | In this research work, low insertion loss, high isolation, ultra-wideband single-pole double-throw (SPDT) switch, single-pole four-throw (SP4T) switch and double-pole double-throw (DPDT) switch matrix are designed with commercial 0.13-μm high-resistivity trap-rich SOI.
Stress memorization technique (SMT) effects on ultra-wideband RF switch performance are investigated for the first time. Compared with the state of the arts, the designed SPDT switch, achieves the lowest insertion loss (< 2.1 dB up to 50 GHz), while the designed SP4T switch achieves the lowest insertion loss (< 2.6 dB) over DC to 35 GHz. The generation1 DPDT switch matrix achieves less than 2.5 dB insertion loss and higher than 32 dB isolation up to 30 GHz. A novel generation2 DPDT switch matrix, which is fabricated on recessed SOI top silicon and connected with through BOX contact (TBC) exhibits less than 2 dB insertion loss and higher than 34 dB isolation from DC to 35 GHz.
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