Power optimization in clock tree synthesis
Among the most challenging tasks of advanced-node IC design is power reduction. In the advanced technology nodes, clock trees have become a prominent source of dynamic power dissipation constituting of almost 15-21 % of the total power dissipation which is about 30-40 mW in the chip dependent on the...
| Main Author: | |
|---|---|
| Other Authors: | |
| Format: | Thesis |
| Language: | English |
| Published: |
2018
|
| Subjects: | |
| Online Access: | http://hdl.handle.net/10356/73133 |