Timing mismatch calibration circuit for high-speed time-interleaved ADCs
The concept of a Time-Interleaved analog-to-digital converter (TI ADC) which comprises sub-ADCs (channels) is proposed as a means of increasing the speed of analog-to-digital converters (ADCs), albeit with a power and area penalty. During the alternate sampling process, timing mismatch between th...
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| Format: | Thesis |
| Language: | English |
| Published: |
2018
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| Online Access: | http://hdl.handle.net/10356/76014 |