Analysis of memory BIST architecture flow
The burgeoning amount and complexity of memories in modern SoC have brought forth new challenges in memory testing. Memory Built-in self-test (BIST) is the most widely used solution for memory testing. MBIST is defined as a method used for insertion of embedded memory controllers inside the chip to...
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| Format: | Thesis |
| Language: | English |
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2018
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| Online Access: | http://hdl.handle.net/10356/76070 |
| _version_ | 1826129516201771008 |
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| author | Sharma, Anmol |
| author2 | Chang Chip Hong |
| author_facet | Chang Chip Hong Sharma, Anmol |
| author_sort | Sharma, Anmol |
| collection | NTU |
| description | The burgeoning amount and complexity of memories in modern SoC have brought forth new challenges in memory testing. Memory Built-in self-test (BIST) is the most widely used solution for memory testing. MBIST is defined as a method used for insertion of embedded memory controllers inside the chip to make its memories fully testable after manufacturing.
This work focusses on implementation of different memory BIST architecture optimization techniques to generate MBIST architectures for given design specifications. These architectures are then compared on the basis of power consumption per memory controller, total cell area and test time required per memory controller. The analysis of these architectures is done to recommend the most optimized MBIST architecture for a given design specification.
This work also provides a comprehensive study of two memory built-in self-test flows which are predominantly used in IC design industry to generate MBIST architecture. The two flows used for this purpose are Tessent Memory BIST LV Flow and Tessent Memory BIST Shell Flow. |
| first_indexed | 2024-10-01T07:41:52Z |
| format | Thesis |
| id | ntu-10356/76070 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T07:41:52Z |
| publishDate | 2018 |
| record_format | dspace |
| spelling | ntu-10356/760702023-07-04T15:39:51Z Analysis of memory BIST architecture flow Sharma, Anmol Chang Chip Hong School of Electrical and Electronic Engineering Technical University of Munich DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits The burgeoning amount and complexity of memories in modern SoC have brought forth new challenges in memory testing. Memory Built-in self-test (BIST) is the most widely used solution for memory testing. MBIST is defined as a method used for insertion of embedded memory controllers inside the chip to make its memories fully testable after manufacturing. This work focusses on implementation of different memory BIST architecture optimization techniques to generate MBIST architectures for given design specifications. These architectures are then compared on the basis of power consumption per memory controller, total cell area and test time required per memory controller. The analysis of these architectures is done to recommend the most optimized MBIST architecture for a given design specification. This work also provides a comprehensive study of two memory built-in self-test flows which are predominantly used in IC design industry to generate MBIST architecture. The two flows used for this purpose are Tessent Memory BIST LV Flow and Tessent Memory BIST Shell Flow. Master of Science (Integrated Circuit Design) 2018-10-22T13:27:18Z 2018-10-22T13:27:18Z 2018 Thesis http://hdl.handle.net/10356/76070 en 116 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits Sharma, Anmol Analysis of memory BIST architecture flow |
| title | Analysis of memory BIST architecture flow |
| title_full | Analysis of memory BIST architecture flow |
| title_fullStr | Analysis of memory BIST architecture flow |
| title_full_unstemmed | Analysis of memory BIST architecture flow |
| title_short | Analysis of memory BIST architecture flow |
| title_sort | analysis of memory bist architecture flow |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Integrated circuits |
| url | http://hdl.handle.net/10356/76070 |
| work_keys_str_mv | AT sharmaanmol analysisofmemorybistarchitectureflow |