Setup and implementation of hierarchical scan insertion using the core wrapping technique
The rapid shrinking of the technology node from deep submicron levels to 90nm and below has allowed the complexity of the designs to increase without significantly increasing the chip size. Large designs are now posing many challenges to all design disciplines including design-for-test (DFT). For a...
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| Format: | Thesis |
| Language: | English |
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2018
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| Online Access: | http://hdl.handle.net/10356/76078 |