A high speed 16-bit CMOS multiplier IC design
In this project, various multiplication algorithms are investigated and used to implement 16-bit CMOS multiplier design. And some common adders are also studied and developed using Verilog HDL language. By using different combination of algorithm and adder, we will study the performance of each 1...
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| Format: | Final Year Project (FYP) |
| Language: | English |
| Published: |
2018
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| Online Access: | http://hdl.handle.net/10356/76261 |