An area- and power-efficient FIFO with error-reduced data compression for image/video processing
Filtering is a key component of many digital image/video processing algorithms. It often requires FIFO to temporarily buffer the pixels data for later usage. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. This paper presents...
| Հիմնական հեղինակներ: | , , , |
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| Այլ հեղինակներ: | |
| Ձևաչափ: | Conference Paper |
| Լեզու: | English |
| Հրապարակվել է: |
2015
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| Խորագրեր: | |
| Առցանց հասանելիություն: | https://hdl.handle.net/10356/79393 http://hdl.handle.net/10220/25887 |
| _version_ | 1826119717224448000 |
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| author | Zeinolabedin, Seyed Mohammad Ali Kim, Tony T. Zhou, Jun Liu, Xin |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Zeinolabedin, Seyed Mohammad Ali Kim, Tony T. Zhou, Jun Liu, Xin |
| author_sort | Zeinolabedin, Seyed Mohammad Ali |
| collection | NTU |
| description | Filtering is a key component of many digital image/video processing algorithms. It often requires FIFO to temporarily buffer the pixels data for later usage. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. This paper presents a technique named FIFO with error-reduced data compression (FERDC) to reduce the FIFO size for various filters. The proposed FERDC significantly reduces the area and power consumption while keeping the error metrics such as mean square error (MSE) and peak signal to noise ratio (PSNR) in the acceptable range. Simulation results of a two dimensional wavelet filter shows that the proposed FERDC technique achieves the FIFO size reduction of up to 44.44% with PSNR values larger than 39 dB, which leads to the reduction of at least 31.6% in the dynamic power and 44.44% in the leakage power. |
| first_indexed | 2024-10-01T05:04:40Z |
| format | Conference Paper |
| id | ntu-10356/79393 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:04:40Z |
| publishDate | 2015 |
| record_format | dspace |
| spelling | ntu-10356/793932020-03-07T13:24:43Z An area- and power-efficient FIFO with error-reduced data compression for image/video processing Zeinolabedin, Seyed Mohammad Ali Kim, Tony T. Zhou, Jun Liu, Xin School of Electrical and Electronic Engineering 2014 IEEE International Symposium on Circuits and Systems (ISCAS) DRNTU::Engineering::Electrical and electronic engineering::Electronic systems Filtering is a key component of many digital image/video processing algorithms. It often requires FIFO to temporarily buffer the pixels data for later usage. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. This paper presents a technique named FIFO with error-reduced data compression (FERDC) to reduce the FIFO size for various filters. The proposed FERDC significantly reduces the area and power consumption while keeping the error metrics such as mean square error (MSE) and peak signal to noise ratio (PSNR) in the acceptable range. Simulation results of a two dimensional wavelet filter shows that the proposed FERDC technique achieves the FIFO size reduction of up to 44.44% with PSNR values larger than 39 dB, which leads to the reduction of at least 31.6% in the dynamic power and 44.44% in the leakage power. Accepted version 2015-06-12T03:32:29Z 2019-12-06T13:24:16Z 2015-06-12T03:32:29Z 2019-12-06T13:24:16Z 2014 2014 Conference Paper Zeinolabedin, S.M.A., Zhou, J., Liu, X., & Kim, T. T. (2014). An area- and power-efficient FIFO with error-reduced data compression for image/video processing. 2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2277-2280. https://hdl.handle.net/10356/79393 http://hdl.handle.net/10220/25887 10.1109/ISCAS.2014.6865625 en © 2015 Institute of Electrical and Electronics Engineers (IEEE). application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems Zeinolabedin, Seyed Mohammad Ali Kim, Tony T. Zhou, Jun Liu, Xin An area- and power-efficient FIFO with error-reduced data compression for image/video processing |
| title | An area- and power-efficient FIFO with error-reduced data compression for image/video processing |
| title_full | An area- and power-efficient FIFO with error-reduced data compression for image/video processing |
| title_fullStr | An area- and power-efficient FIFO with error-reduced data compression for image/video processing |
| title_full_unstemmed | An area- and power-efficient FIFO with error-reduced data compression for image/video processing |
| title_short | An area- and power-efficient FIFO with error-reduced data compression for image/video processing |
| title_sort | area and power efficient fifo with error reduced data compression for image video processing |
| topic | DRNTU::Engineering::Electrical and electronic engineering::Electronic systems |
| url | https://hdl.handle.net/10356/79393 http://hdl.handle.net/10220/25887 |
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