An area- and power-efficient FIFO with error-reduced data compression for image/video processing

An area- and power-efficient FIFO with error-reduced data compression for image/video processing

Filtering is a key component of many digital image/video processing algorithms. It often requires FIFO to temporarily buffer the pixels data for later usage. The FIFO size is proportional to the length of the filters and input data width, causing large area and power consumption. This paper presents...

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Bibliographic Details
Main Authors: Zeinolabedin, Seyed Mohammad Ali, Kim, Tony T., Zhou, Jun, Liu, Xin
Other Authors: School of Electrical and Electronic Engineering
Format: Conference Paper
Language:English
Published: 2015
Subjects:
DRNTU::Engineering::Electrical and electronic engineering::Electronic systems
Online Access:https://hdl.handle.net/10356/79393
http://hdl.handle.net/10220/25887

Internet

https://hdl.handle.net/10356/79393
http://hdl.handle.net/10220/25887

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