Power and area efficient clock stretching and critical path reshaping for error resilience
Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to...
| 主要な著者: | , , |
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| その他の著者: | |
| フォーマット: | Journal Article |
| 言語: | English |
| 出版事項: |
2019
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| 主題: | |
| オンライン･アクセス: | https://hdl.handle.net/10356/79534 http://hdl.handle.net/10220/49055 |