Power and area efficient clock stretching and critical path reshaping for error resilience
Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to...
| Main Authors: | , , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2019
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| Online Access: | https://hdl.handle.net/10356/79534 http://hdl.handle.net/10220/49055 |
| _version_ | 1811676703019237376 |
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| author | Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung |
| author_sort | Jayakrishnan, Mini |
| collection | NTU |
| description | Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively. |
| first_indexed | 2024-10-01T02:25:41Z |
| format | Journal Article |
| id | ntu-10356/79534 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T02:25:41Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/795342020-03-07T13:57:22Z Power and area efficient clock stretching and critical path reshaping for error resilience Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung School of Electrical and Electronic Engineering VIRTUS, IC Design Centre of Excellence Better Than Worst Case Design Error Tolerance DRNTU::Engineering::Electrical and electronic engineering Energy efficient semiconductor chips are in high demand to cater the needs of today’s smart products. Advanced technology nodes insert high design margins to deal with rising variations at the cost of power, area and performance. Existing run time resilience techniques are not cost effective due to the additional circuits involved. In this paper, we propose a design time resilience technique using a clock stretched flip-flop to redistribute the available slack in the processor pipeline to the critical paths. We use the opportunistic slack to redesign the critical fan in logic using logic reshaping, better than worst case sigma corner libraries and multi-bit flip-flops to achieve power and area savings. Experimental results prove that we can tune the logic and the library to get significant power and area savings of 69% and 15% in the execute pipeline stage of the processor compared to the traditional worst-case design. Whereas, existing run time resilience hardware results in 36% and 2% power and area overhead respectively. Published version 2019-07-01T08:19:10Z 2019-12-06T13:27:38Z 2019-07-01T08:19:10Z 2019-12-06T13:27:38Z 2019 Journal Article Jayakrishnan, M., Chang, A., & Kim, T. T.-H. (2019). Power and area efficient clock stretching and critical path reshaping for error resilience. Journal of Low Power Electronics and Applications, 9(1), 5-. doi:10.3390/jlpea9010005 2079-9268 https://hdl.handle.net/10356/79534 http://hdl.handle.net/10220/49055 10.3390/jlpea9010005 en Journal of Low Power Electronics and Applications © 2019 The Authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/). 16 p. application/pdf |
| spellingShingle | Better Than Worst Case Design Error Tolerance DRNTU::Engineering::Electrical and electronic engineering Jayakrishnan, Mini Chang, Alan Kim, Tony Tae-Hyoung Power and area efficient clock stretching and critical path reshaping for error resilience |
| title | Power and area efficient clock stretching and critical path reshaping for error resilience |
| title_full | Power and area efficient clock stretching and critical path reshaping for error resilience |
| title_fullStr | Power and area efficient clock stretching and critical path reshaping for error resilience |
| title_full_unstemmed | Power and area efficient clock stretching and critical path reshaping for error resilience |
| title_short | Power and area efficient clock stretching and critical path reshaping for error resilience |
| title_sort | power and area efficient clock stretching and critical path reshaping for error resilience |
| topic | Better Than Worst Case Design Error Tolerance DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/79534 http://hdl.handle.net/10220/49055 |
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