Heterogeneous dataflow architectures for FPGA-based sparse LU factorization
FPGA-based token dataflow architectures with heterogeneous computation and communication subsystems can accelerate hard-to-parallelize, irregular computations in sparse LU factorization. We combine software pre-processing and architecture customization to fully expose and exploit the underlying hete...
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| 格式: | Conference Paper |
| 语言: | English |
| 出版: |
2015
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| 在线阅读: | https://hdl.handle.net/10356/81188 http://hdl.handle.net/10220/39175 |