Driving Timing Convergence of FPGA Designs through Machine Learning and Cloud Computing
Machine learning and cloud computing techniques can help accelerate timing closure for FPGA designs without any modification to original RTL code. RTL is generally frozen closer to system delivery target to avoid injecting new unforeseen bugs or significantly affecting design characteristics. In the...
| Main Authors: | , , , |
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| 格式: | Conference Paper |
| 语言: | English |
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2015
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| 主题: | |
| 在线阅读: | https://hdl.handle.net/10356/81244 http://hdl.handle.net/10220/39167 |