Transistor/gate level reliability modeling
The development of CMOS technology is a double-edged sword: for one thing, it provides faster,lowerpower-consuming,and smaller-size devices; for another,reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) become severer, resulting in device/gate pe...
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| Format: | Thesis |
| Language: | English |
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2019
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| Online Access: | https://hdl.handle.net/10356/82933 http://hdl.handle.net/10220/47536 |