Transistor/gate level reliability modeling
The development of CMOS technology is a double-edged sword: for one thing, it provides faster,lowerpower-consuming,and smaller-size devices; for another,reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) become severer, resulting in device/gate pe...
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| Format: | Thesis |
| Language: | English |
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2019
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| Online Access: | https://hdl.handle.net/10356/82933 http://hdl.handle.net/10220/47536 |
| _version_ | 1811691488931741696 |
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| author | Liu, Xu |
| author2 | Zhou Xing |
| author_facet | Zhou Xing Liu, Xu |
| author_sort | Liu, Xu |
| collection | NTU |
| description | The development of CMOS technology is a double-edged sword: for one thing, it provides faster,lowerpower-consuming,and smaller-size devices; for another,reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) become severer, resulting in device/gate performance degradation. Compact and accurate modelling of these issues is equired in aid of IC design. Reliability modelling could be done at the transistor level: the device parameter shift ∆p(such as the threshold voltage ∆Vth) or performance (for example, the current Ion) shift are described as time-related (tstress) functions.
At the gate level, the delay degradation is obtained with the insertion of the transistor-level parameter/performance shift equations. The timing analysis at the gate level is done with methods such as the static timing analysis (STA) rather than the time-consuming SPICE simulation, but the latter could be adopted for characterisation owing to its accuracy. The reliability models at the transistor level and the gate level interact with each other: the gate level model takes ∆p as an input, which must be derived from the transistor level model; the transistor level model determines ∆p with the value of tstress, which is a statistical parameter in the gate level model. The models achieve three goals: simplicity, time efficiency, and accuracy. The gate model called ”Aging-Gate” has been built up to take both NBTI ( ∆Vth) and HCI ( ∆Ion) into account; algorithms for tstress determination could be adopted for transistor level modelling.
To simplify this model, HCI is also modelled with ∆Vth such that the gate model equations could be simplified.
A surface-potential (øs)-based transistor model is also available, and tstress is to be incorporated in for ∆Vth determination. The so called ”recovery effect” in NBTI results in iterative methods that suffer from time-efficiency problems. The new model provides a compact algorithm that achieves equivalent accuracy, which significantly improves the time efficiency. To ensure the efficiency, the original Aging-Gate model ignores the recovery effect by adopting a simple DC NBTI model, but this leads to overestimation of the delay degradation. The new model alleviates this since the "recovery effect" is considered, yet the time efficiency is maintained in that the new model is as fast as the DC model. Therefore, the accuracy is improved. |
| first_indexed | 2024-10-01T06:20:42Z |
| format | Thesis |
| id | ntu-10356/82933 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T06:20:42Z |
| publishDate | 2019 |
| record_format | dspace |
| spelling | ntu-10356/829332023-07-04T16:26:16Z Transistor/gate level reliability modeling Liu, Xu Zhou Xing School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering The development of CMOS technology is a double-edged sword: for one thing, it provides faster,lowerpower-consuming,and smaller-size devices; for another,reliability issues such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) become severer, resulting in device/gate performance degradation. Compact and accurate modelling of these issues is equired in aid of IC design. Reliability modelling could be done at the transistor level: the device parameter shift ∆p(such as the threshold voltage ∆Vth) or performance (for example, the current Ion) shift are described as time-related (tstress) functions. At the gate level, the delay degradation is obtained with the insertion of the transistor-level parameter/performance shift equations. The timing analysis at the gate level is done with methods such as the static timing analysis (STA) rather than the time-consuming SPICE simulation, but the latter could be adopted for characterisation owing to its accuracy. The reliability models at the transistor level and the gate level interact with each other: the gate level model takes ∆p as an input, which must be derived from the transistor level model; the transistor level model determines ∆p with the value of tstress, which is a statistical parameter in the gate level model. The models achieve three goals: simplicity, time efficiency, and accuracy. The gate model called ”Aging-Gate” has been built up to take both NBTI ( ∆Vth) and HCI ( ∆Ion) into account; algorithms for tstress determination could be adopted for transistor level modelling. To simplify this model, HCI is also modelled with ∆Vth such that the gate model equations could be simplified. A surface-potential (øs)-based transistor model is also available, and tstress is to be incorporated in for ∆Vth determination. The so called ”recovery effect” in NBTI results in iterative methods that suffer from time-efficiency problems. The new model provides a compact algorithm that achieves equivalent accuracy, which significantly improves the time efficiency. To ensure the efficiency, the original Aging-Gate model ignores the recovery effect by adopting a simple DC NBTI model, but this leads to overestimation of the delay degradation. The new model alleviates this since the "recovery effect" is considered, yet the time efficiency is maintained in that the new model is as fast as the DC model. Therefore, the accuracy is improved. Doctor of Philosophy 2019-01-22T05:44:36Z 2019-12-06T15:08:34Z 2019-01-22T05:44:36Z 2019-12-06T15:08:34Z 2018 Thesis Liu, X. (2018). Transistor/gate level reliability modeling. Doctoral thesis, Nanyang Technological University, Singapore. https://hdl.handle.net/10356/82933 http://hdl.handle.net/10220/47536 10.32657/10220/47536 en 136 p. application/pdf |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering Liu, Xu Transistor/gate level reliability modeling |
| title | Transistor/gate level reliability modeling |
| title_full | Transistor/gate level reliability modeling |
| title_fullStr | Transistor/gate level reliability modeling |
| title_full_unstemmed | Transistor/gate level reliability modeling |
| title_short | Transistor/gate level reliability modeling |
| title_sort | transistor gate level reliability modeling |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/82933 http://hdl.handle.net/10220/47536 |
| work_keys_str_mv | AT liuxu transistorgatelevelreliabilitymodeling |