Evaluating the efficiency of DSP Block synthesis inference from flow graphs
The embedded DSP Blocks in FPGAs have become significantly more capable in recent generations of devices. While vendor synthesis tools can infer the use of these resources, the efficiency of this inference is not guaranteed. Specific language structures are suggested for implementing standard applic...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2013
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| Online Access: | https://hdl.handle.net/10356/83937 http://hdl.handle.net/10220/12874 |