Low Normalized Energy Derivation Asynchronous Circuit Synthesis Flow through Fork-Join Slack Matching for Cryptographic Applications
In this paper, an automatic synthesis flow of asynchronous (async) Quasi-Delay-Insensitive (QDI) circuits for cryptographic applications is presented. The synthesis flow accepts Verilog netlists as primary inputs, in part leverages on commercial electronic design automation tools for synthesis and v...
Main Authors: | , , , , |
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Other Authors: | |
Format: | Conference Paper |
Language: | English |
Published: |
2017
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Subjects: | |
Online Access: | https://hdl.handle.net/10356/84004 http://hdl.handle.net/10220/42123 http://ieeexplore.ieee.org/document/7459427/ |