High-speed and low-power serial accumulator for serial/parallel multiplier
This paper presents a new approach to serial/parallel multiplier design by using parallel 1's counters to accumulate the binary partial product bits. The 1's in each column of the partial product matrix due to the serially input operands are accumulated using a serial T-flip flop (TFF) cou...
| Main Authors: | , , |
|---|---|
| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2010
|
| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/90594 http://hdl.handle.net/10220/6353 |