Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

Physical layout design optimization of integrated spiral inductors for silicon-based RFIC applications

A new test structure layout technique and design methodology are used to investigate quantitatively how geometrical layout parameters such as core diameter, conductor spacing, and width would affect the performance of spiral inductors. For the 0.18-µm RFCMOS technology, experimental results in this...

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Bibliographic Details
Main Authors: Sia, Choon Beng, Ong, Beng Hwee, Chan, Kwok Wai, Yeo, Kiat Seng, Ma, Jianguo, Do, Manh Anh
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2009
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/91514
http://hdl.handle.net/10220/4663

Internet

https://hdl.handle.net/10356/91514
http://hdl.handle.net/10220/4663

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