Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides

Effect of the trapped Si ions in a 30-nm gate oxide implanted with Si+ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700°C for 20 min, although only 0.1 per cent of the implanted Si ions remained, it can cause a flatban...

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Main Authors: Chen, Q., Zhao, P., Tseng, Ampere A., Ng, Chi Yung, Chen, Tupei, Ding, Liang, Liu, Yang, Fung, Stevenson Hon Yuen
Other Authors: School of Electrical and Electronic Engineering
Format: Journal Article
Language:English
Published: 2010
Subjects:
Online Access:https://hdl.handle.net/10356/92134
http://hdl.handle.net/10220/6405
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author Chen, Q.
Zhao, P.
Tseng, Ampere A.
Ng, Chi Yung
Chen, Tupei
Ding, Liang
Liu, Yang
Fung, Stevenson Hon Yuen
author2 School of Electrical and Electronic Engineering
author_facet School of Electrical and Electronic Engineering
Chen, Q.
Zhao, P.
Tseng, Ampere A.
Ng, Chi Yung
Chen, Tupei
Ding, Liang
Liu, Yang
Fung, Stevenson Hon Yuen
author_sort Chen, Q.
collection NTU
description Effect of the trapped Si ions in a 30-nm gate oxide implanted with Si+ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700°C for 20 min, although only 0.1 per cent of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900°C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900°C for 20 min is sufficient for eliminating the effect of the trapped ions.
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spelling ntu-10356/921342020-03-07T13:57:24Z Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides Chen, Q. Zhao, P. Tseng, Ampere A. Ng, Chi Yung Chen, Tupei Ding, Liang Liu, Yang Fung, Stevenson Hon Yuen School of Electrical and Electronic Engineering DRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials Effect of the trapped Si ions in a 30-nm gate oxide implanted with Si+ at a very low energy (1.3 keV) on the flatband voltage after various thermal annealing has been examined. For the annealing at 700°C for 20 min, although only 0.1 per cent of the implanted Si ions remained, it can cause a flatband voltage shift of -21.3 V, and the flatband voltage shift reduces with time under a negative gate voltage showing neutralization of the trapped ions by the injected electrons from the gate. However, the annealing at 900°C for 20 min has reduced the number of the remaining ions to the lowest limit corresponding to a flatband voltage shift of -0.1 V, and the application of the negative voltage does not change the flatband voltage. A higher annealing temperature or a longer annealing time does not show further improvement, suggesting that the annealing at 900°C for 20 min is sufficient for eliminating the effect of the trapped ions. Published version 2010-09-06T02:52:04Z 2019-12-06T18:18:02Z 2010-09-06T02:52:04Z 2019-12-06T18:18:02Z 2006 2006 Journal Article Chen, Q., Zhao, P., Tseng, A. A., Ng, C. Y., Chen T. P., Ding, L., et al. (2006). Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides. IEEE Transactions on Electron Devices, 53(5), 1280-1282. 0018-9383 https://hdl.handle.net/10356/92134 http://hdl.handle.net/10220/6405 10.1109/TED.2006.871841 en IEEE transactions on electron devices © 2006 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. http://www.ieee.org/portal/site This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. 3 p. application/pdf
spellingShingle DRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials
Chen, Q.
Zhao, P.
Tseng, Ampere A.
Ng, Chi Yung
Chen, Tupei
Ding, Liang
Liu, Yang
Fung, Stevenson Hon Yuen
Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides
title Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides
title_full Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides
title_fullStr Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides
title_full_unstemmed Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides
title_short Si ion-induced instability in flatband voltage of Si+ -implanted gate oxides
title_sort si ion induced instability in flatband voltage of si implanted gate oxides
topic DRNTU::Engineering::Electrical and electronic engineering::Electronic apparatus and materials
url https://hdl.handle.net/10356/92134
http://hdl.handle.net/10220/6405
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