Dual nanowire silicon MOSFET with silicon bridge and TaN gate
This paper demonstrates a high performance silicon nanowire mosfet built on silicon-on-insulator (SOI) platform. Stress-limiting oxidation technique was exploited for dual nanowire channel formation. To further improve the performance of the device, TaN metal gate is used instead of the conventional...
| Auteurs principaux: | , , , , |
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| Autres auteurs: | |
| Format: | Journal Article |
| Langue: | English |
| Publié: |
2010
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| Sujets: | |
| Accès en ligne: | https://hdl.handle.net/10356/92303 http://hdl.handle.net/10220/6263 |