An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit
This paper describes an 8-bit pipelined analog-to-digital converter (ADC) using a mixed-mode sample-and-hold (S/H)circuit at the front-end. The mixed-mode sampling technique reduces signal swings in pipelined ADCs while maintaining the signal-to-noise ratio. The reduction of signal swings relaxes th...
| Главные авторы: | , , , |
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| Другие авторы: | |
| Формат: | Journal Article |
| Язык: | English |
| Опубликовано: |
2010
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| Предметы: | |
| Online-ссылка: | https://hdl.handle.net/10356/92397 http://hdl.handle.net/10220/6256 |