A Low-Jitter Polyphase-Filter-Based frequency multiplier with phase error calibration
A new low-jitter polyphase-filter-based frequency multiplier incorporating a phase error calibration circuit to reduce the phase errors is presented. Designing with a multiplication ratio of eight, it has been fabricated in a 0.13- m CMOS process....
| Автори: | , |
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| Інші автори: | |
| Формат: | Journal Article |
| Мова: | English |
| Опубліковано: |
2010
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| Предмети: | |
| Онлайн доступ: | https://hdl.handle.net/10356/92971 http://hdl.handle.net/10220/6253 |