An enhanced low-power high-speed adder for error-tolerant application

An enhanced low-power high-speed adder for error-tolerant application

The occurrence of errors are inevitable in modern VLSI technology and to overcome all possible errors is an expensive task. It not only consumes a lot of power but degrades the speed performance. By adopting an emerging concept in VLSI desi...

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Bibliographic Details
Main Authors: Zhu, Ning, Goh, Wang Ling, Yeo, Kiat Seng
Other Authors: School of Electrical and Electronic Engineering
Format: Conference Paper
Language:English
Published: 2010
Subjects:
DRNTU::Engineering::Electrical and electronic engineering
Online Access:https://hdl.handle.net/10356/93564
http://hdl.handle.net/10220/6350
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403865

Internet

https://hdl.handle.net/10356/93564
http://hdl.handle.net/10220/6350
http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=5403865

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