Effect of IC layout on the reliability of CMOS amplifiers
With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the eff...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Journal Article |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/98538 http://hdl.handle.net/10220/11171 |
| _version_ | 1811687079098187776 |
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| author | He, Feifei Tan, Cher Ming |
| author2 | School of Electrical and Electronic Engineering |
| author_facet | School of Electrical and Electronic Engineering He, Feifei Tan, Cher Ming |
| author_sort | He, Feifei |
| collection | NTU |
| description | With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs. |
| first_indexed | 2024-10-01T05:10:36Z |
| format | Journal Article |
| id | ntu-10356/98538 |
| institution | Nanyang Technological University |
| language | English |
| last_indexed | 2024-10-01T05:10:36Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | ntu-10356/985382020-03-07T14:00:30Z Effect of IC layout on the reliability of CMOS amplifiers He, Feifei Tan, Cher Ming School of Electrical and Electronic Engineering A*STAR SIMTech DRNTU::Engineering::Electrical and electronic engineering With shrinking device size and increasing circuit complexity, interconnect reliability has become the main factor that affects the integrated circuit (IC) reliability. Electromigration (EM) is the major failure mechanism for interconnect reliability. However, little research had been done on the effect of IC layout on the void nucleation time (i.e. the time where the vacancies in the metal gather and nucleate into a tiny void) in the interconnections of the circuits due to electromigration using 3D modeling. In this paper, we construct the 3D models for a CMOS class-AB amplifier and a RF low noise amplifier (LNA), and investigate the impact of layout design on the void nucleation time through the computation of the atomic flux divergence (AFD) of the 3D circuit models. From the simulation results we find that, there is a change in the value of the maximum total AFD with the change in the number of contacts or the inter-transistor distance. A change in the location of the maximum total AFD is observed in the LNA circuit with different finger number as a result of the change in the line width and the transistor rotation. This indicates a different reliability lifetime and void formation location with different layout designs. 2013-07-11T02:55:02Z 2019-12-06T19:56:37Z 2013-07-11T02:55:02Z 2019-12-06T19:56:37Z 2011 2011 Journal Article https://hdl.handle.net/10356/98538 http://hdl.handle.net/10220/11171 10.1016/j.microrel.2011.11.010 en Microelectronics reliability © 2011 Elsevier Ltd. |
| spellingShingle | DRNTU::Engineering::Electrical and electronic engineering He, Feifei Tan, Cher Ming Effect of IC layout on the reliability of CMOS amplifiers |
| title | Effect of IC layout on the reliability of CMOS amplifiers |
| title_full | Effect of IC layout on the reliability of CMOS amplifiers |
| title_fullStr | Effect of IC layout on the reliability of CMOS amplifiers |
| title_full_unstemmed | Effect of IC layout on the reliability of CMOS amplifiers |
| title_short | Effect of IC layout on the reliability of CMOS amplifiers |
| title_sort | effect of ic layout on the reliability of cmos amplifiers |
| topic | DRNTU::Engineering::Electrical and electronic engineering |
| url | https://hdl.handle.net/10356/98538 http://hdl.handle.net/10220/11171 |
| work_keys_str_mv | AT hefeifei effectoficlayoutonthereliabilityofcmosamplifiers AT tancherming effectoficlayoutonthereliabilityofcmosamplifiers |