A 1.2 V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver
This paper presents a low power 1.2 V, 2.4 GHz low spur, Quadrature PLL synthesizer for IEEE 802.15.4 batteryless transceiver in CMOS 0.18 μm technology. The PLL employs a 1 MHz fully programmable divider with an improved CML 2/3 prescaler, a novel bit-cell for the programmable counters and a novel...
| Main Authors: | , , , , , |
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| 其他作者: | |
| 格式: | Conference Paper |
| 语言: | English |
| 出版: |
2013
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| 主题: | |
| 在线阅读: | https://hdl.handle.net/10356/98803 http://hdl.handle.net/10220/12776 |