A 1.2 V 2.4 GHz low spur CMOS PLL synthesizer with a gain boosted charge pump for a batteryless transceiver
This paper presents a low power 1.2 V, 2.4 GHz low spur, Quadrature PLL synthesizer for IEEE 802.15.4 batteryless transceiver in CMOS 0.18 μm technology. The PLL employs a 1 MHz fully programmable divider with an improved CML 2/3 prescaler, a novel bit-cell for the programmable counters and a novel...
| Main Authors: | , , , , , |
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| Other Authors: | |
| Format: | Conference Paper |
| Language: | English |
| Published: |
2013
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| Subjects: | |
| Online Access: | https://hdl.handle.net/10356/98803 http://hdl.handle.net/10220/12776 |
| Summary: | This paper presents a low power 1.2 V, 2.4 GHz low spur, Quadrature PLL synthesizer for IEEE 802.15.4 batteryless transceiver in CMOS 0.18 μm technology. The PLL employs a 1 MHz fully programmable divider with an improved CML 2/3 prescaler, a novel bit-cell for the programmable counters and a novel charge pump with gain-boosted technique to reduce the PLL reference spurs. The PLL consumes a power of 1.85 mW at 1.2 V power supply with the programmable divider consuming only 350 μW. The phase noise of the PLL is -112.77 dBc/Hz at 1 MHz offset and the spurs are -46.2 dB below the carrier and the PLL is successfully tested with the energy harvesting circuit. |
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