FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD)
Equation-Defined Device models (EDD) have become very popular for behavioural modelling of semiconductor and other non-linear devices. Two feature that makes them particularly attractive are their interactive nature and easy testing during the model development process. However, they are less suited...
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| Format: | Conference or Workshop Item |
| Language: | English English |
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IEEE
2019
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| Online Access: | https://repository.londonmet.ac.uk/5237/1/MIXDESSlides2019.pdf https://repository.londonmet.ac.uk/5237/7/mixdes2019.pdf |
| _version_ | 1824446419216367616 |
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| author | Brinson, Mike |
| author_facet | Brinson, Mike |
| author_sort | Brinson, Mike |
| collection | LMU |
| description | Equation-Defined Device models (EDD) have become very popular for behavioural modelling of semiconductor and other non-linear devices. Two feature that makes them particularly attractive are their interactive nature and easy testing during the model development process. However, they are less suited for operation as production level models due to their slow simulation performance. This paper presents a new extension to the EDD that offers C++ model performance coupled with the convenience of EDD modelling. The extended form of the EDD is called a Verilog-A EDD or VAEDD for short. It has the same structure as the standard EDD but is built around compiled Verilog-A module code, which in turn is translated to C++ code and dynamically linked to the main body of the simulator code. Essentially a VAEDD is a tiny Verilog-A module with a standardised internal code structure. To demonstrate the interactive approach to compact model building with VAEDD components the design and testing of a high power SiC Schottky barrier diode is included in the main body of the text. |
| first_indexed | 2024-07-09T03:59:07Z |
| format | Conference or Workshop Item |
| id | oai:repository.londonmet.ac.uk:5237 |
| institution | London Metropolitan University |
| language | English English |
| last_indexed | 2024-07-09T03:59:07Z |
| publishDate | 2019 |
| publisher | IEEE |
| record_format | eprints |
| spelling | oai:repository.londonmet.ac.uk:52372020-07-06T11:40:59Z http://repository.londonmet.ac.uk/5237/ FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD) Brinson, Mike 620 Engineering & allied operations Equation-Defined Device models (EDD) have become very popular for behavioural modelling of semiconductor and other non-linear devices. Two feature that makes them particularly attractive are their interactive nature and easy testing during the model development process. However, they are less suited for operation as production level models due to their slow simulation performance. This paper presents a new extension to the EDD that offers C++ model performance coupled with the convenience of EDD modelling. The extended form of the EDD is called a Verilog-A EDD or VAEDD for short. It has the same structure as the standard EDD but is built around compiled Verilog-A module code, which in turn is translated to C++ code and dynamically linked to the main body of the simulator code. Essentially a VAEDD is a tiny Verilog-A module with a standardised internal code structure. To demonstrate the interactive approach to compact model building with VAEDD components the design and testing of a high power SiC Schottky barrier diode is included in the main body of the text. IEEE 2019-06-27 Conference or Workshop Item PeerReviewed text en cc_by_nd_4 https://repository.londonmet.ac.uk/5237/1/MIXDESSlides2019.pdf text en https://repository.londonmet.ac.uk/5237/7/mixdes2019.pdf Brinson, Mike (2019) FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD). In: 26th International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 27-29 June 2019, Rzeszow, Poland. https://ieeexplore.ieee.org/xpl/conhome/8777447/proceeding 10.23919/MIXDES.2019.8787063 |
| spellingShingle | 620 Engineering & allied operations Brinson, Mike FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD) |
| title | FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD) |
| title_full | FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD) |
| title_fullStr | FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD) |
| title_full_unstemmed | FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD) |
| title_short | FOSS Compact Model Prototyping with Verilog-A Equation-Defined Devices (VAEDD) |
| title_sort | foss compact model prototyping with verilog a equation defined devices vaedd |
| topic | 620 Engineering & allied operations |
| url | https://repository.londonmet.ac.uk/5237/1/MIXDESSlides2019.pdf https://repository.londonmet.ac.uk/5237/7/mixdes2019.pdf |
| work_keys_str_mv | AT brinsonmike fosscompactmodelprototypingwithverilogaequationdefineddevicesvaedd |