A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing
Three dimensional (3D) stacking of memory chips is a promising direction for implementing memory systems in mobile applications [1-2] and for low-cost high-performance computation [3]. The requirements are extremely low power consumption, high data bandwidth, stability and scalability of operation,...
| Autores principales: | , , , , , , |
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| Formato: | Conference item |
| Publicado: |
2013
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| _version_ | 1826256699275608064 |
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| author | Takaya, S Nagata, M Sakai, A Kariya, T Uchiyama, S Kobayashi, H Ikeda, H |
| author_facet | Takaya, S Nagata, M Sakai, A Kariya, T Uchiyama, S Kobayashi, H Ikeda, H |
| author_sort | Takaya, S |
| collection | OXFORD |
| description | Three dimensional (3D) stacking of memory chips is a promising direction for implementing memory systems in mobile applications [1-2] and for low-cost high-performance computation [3]. The requirements are extremely low power consumption, high data bandwidth, stability and scalability of operation, as well as large storage capacity with a small footprint. A digital control chip at the base of the stack is needed to efficiently access the 3D memory hierarchy, as well as to emulate a standard memory interface for compatibility. The overall performance and yields of a 3D system are constrained by vertical communication channels among the stacked chips, as well as the connections to the PCB. However, the empirical models presently used in the design stage do not properly represent the electrical and mechanical properties and performance variations of through silicon vias (TSVs) and microbumps (μBumps). What is needed are circuit techniques that handle such uncertainties to enable the creation of robust 3D data links. This paper presents a complete test vehicle for TSV-based wide I/O data communication in a three-tier 3D chip stack assembled in a BGA package. In-place eye-diagram and waveform capturers are mounted in an active silicon interposer to characterize vertical signaling through the chain of TSVs and μBumps. © 2013 IEEE. |
| first_indexed | 2024-03-06T18:06:23Z |
| format | Conference item |
| id | oxford-uuid:018d5209-1bc5-484d-b04e-4ac4165ca572 |
| institution | University of Oxford |
| last_indexed | 2024-03-06T18:06:23Z |
| publishDate | 2013 |
| record_format | dspace |
| spelling | oxford-uuid:018d5209-1bc5-484d-b04e-4ac4165ca5722022-03-26T08:35:43ZA 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturingConference itemhttp://purl.org/coar/resource_type/c_5794uuid:018d5209-1bc5-484d-b04e-4ac4165ca572Symplectic Elements at Oxford2013Takaya, SNagata, MSakai, AKariya, TUchiyama, SKobayashi, HIkeda, HThree dimensional (3D) stacking of memory chips is a promising direction for implementing memory systems in mobile applications [1-2] and for low-cost high-performance computation [3]. The requirements are extremely low power consumption, high data bandwidth, stability and scalability of operation, as well as large storage capacity with a small footprint. A digital control chip at the base of the stack is needed to efficiently access the 3D memory hierarchy, as well as to emulate a standard memory interface for compatibility. The overall performance and yields of a 3D system are constrained by vertical communication channels among the stacked chips, as well as the connections to the PCB. However, the empirical models presently used in the design stage do not properly represent the electrical and mechanical properties and performance variations of through silicon vias (TSVs) and microbumps (μBumps). What is needed are circuit techniques that handle such uncertainties to enable the creation of robust 3D data links. This paper presents a complete test vehicle for TSV-based wide I/O data communication in a three-tier 3D chip stack assembled in a BGA package. In-place eye-diagram and waveform capturers are mounted in an active silicon interposer to characterize vertical signaling through the chain of TSVs and μBumps. © 2013 IEEE. |
| spellingShingle | Takaya, S Nagata, M Sakai, A Kariya, T Uchiyama, S Kobayashi, H Ikeda, H A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing |
| title | A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing |
| title_full | A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing |
| title_fullStr | A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing |
| title_full_unstemmed | A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing |
| title_short | A 100GB/s wide I/O with 4096b TSVs through an active silicon interposer with in-place waveform capturing |
| title_sort | 100gb s wide i o with 4096b tsvs through an active silicon interposer with in place waveform capturing |
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