Formal techniques for effective co-verification of hardware/software co-designs
Verification is indispensable for building reliable of hardware/software co-designs. However, the scope of formal methods in this domain is limited. This is attributed to the lack of unified property specification languages, the semantic gap between hardware and software components, and the lack of...
| Main Authors: | , , , |
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| Format: | Conference item |
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Association for Computing Machinery
2017
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