Pipeline quantum processor architecture for silicon spin qubits
We propose a quantum processor architecture, the qubit ‘pipeline’, in which run-time scales additively as functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity of control and interconnect resources. This simplification is achieved by shuttling...
| Main Authors: | , , , , , |
|---|---|
| Format: | Journal article |
| Language: | English |
| Published: |
Springer Nature
2024
|
| _version_ | 1826313144160485376 |
|---|---|
| author | Patomäki, SM Gonzalez-Zalba, MF Fogarty, MA Cai, Z Benjamin, SC Morton, JJL |
| author_facet | Patomäki, SM Gonzalez-Zalba, MF Fogarty, MA Cai, Z Benjamin, SC Morton, JJL |
| author_sort | Patomäki, SM |
| collection | OXFORD |
| description | We propose a quantum processor architecture, the qubit ‘pipeline’, in which run-time scales additively as functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity of control and interconnect resources. This simplification is achieved by shuttling N-qubit states through a large layered physical array of structures which realise quantum logic gates in stages. Thus, the circuit depth corresponds to the number of layers of structures. Subsequent N-qubit states are ‘pipelined’ densely through the structures to efficiently wield the physical resources for repeated runs. Pipelining thus lends itself to noisy intermediate-scale quantum (NISQ) applications, such as variational quantum eigensolvers, which require numerous repetitions of the same or similar calculations. We illustrate the architecture by describing a realisation in the naturally high-density and scalable silicon spin qubit platform, which includes a universal gate set of sufficient fidelity under realistic assumptions of qubit variability. |
| first_indexed | 2024-09-25T04:06:38Z |
| format | Journal article |
| id | oxford-uuid:2df7e6ad-0e89-47b7-bc76-9708a1448265 |
| institution | University of Oxford |
| language | English |
| last_indexed | 2024-09-25T04:06:38Z |
| publishDate | 2024 |
| publisher | Springer Nature |
| record_format | dspace |
| spelling | oxford-uuid:2df7e6ad-0e89-47b7-bc76-9708a14482652024-06-05T10:11:00ZPipeline quantum processor architecture for silicon spin qubitsJournal articlehttp://purl.org/coar/resource_type/c_dcae04bcuuid:2df7e6ad-0e89-47b7-bc76-9708a1448265EnglishSymplectic ElementsSpringer Nature2024Patomäki, SMGonzalez-Zalba, MFFogarty, MACai, ZBenjamin, SCMorton, JJLWe propose a quantum processor architecture, the qubit ‘pipeline’, in which run-time scales additively as functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity of control and interconnect resources. This simplification is achieved by shuttling N-qubit states through a large layered physical array of structures which realise quantum logic gates in stages. Thus, the circuit depth corresponds to the number of layers of structures. Subsequent N-qubit states are ‘pipelined’ densely through the structures to efficiently wield the physical resources for repeated runs. Pipelining thus lends itself to noisy intermediate-scale quantum (NISQ) applications, such as variational quantum eigensolvers, which require numerous repetitions of the same or similar calculations. We illustrate the architecture by describing a realisation in the naturally high-density and scalable silicon spin qubit platform, which includes a universal gate set of sufficient fidelity under realistic assumptions of qubit variability. |
| spellingShingle | Patomäki, SM Gonzalez-Zalba, MF Fogarty, MA Cai, Z Benjamin, SC Morton, JJL Pipeline quantum processor architecture for silicon spin qubits |
| title | Pipeline quantum processor architecture for silicon spin qubits |
| title_full | Pipeline quantum processor architecture for silicon spin qubits |
| title_fullStr | Pipeline quantum processor architecture for silicon spin qubits |
| title_full_unstemmed | Pipeline quantum processor architecture for silicon spin qubits |
| title_short | Pipeline quantum processor architecture for silicon spin qubits |
| title_sort | pipeline quantum processor architecture for silicon spin qubits |
| work_keys_str_mv | AT patomakism pipelinequantumprocessorarchitectureforsiliconspinqubits AT gonzalezzalbamf pipelinequantumprocessorarchitectureforsiliconspinqubits AT fogartyma pipelinequantumprocessorarchitectureforsiliconspinqubits AT caiz pipelinequantumprocessorarchitectureforsiliconspinqubits AT benjaminsc pipelinequantumprocessorarchitectureforsiliconspinqubits AT mortonjjl pipelinequantumprocessorarchitectureforsiliconspinqubits |