Pipeline quantum processor architecture for silicon spin qubits
We propose a quantum processor architecture, the qubit ‘pipeline’, in which run-time scales additively as functions of circuit depth and run repetitions. Run-time control is applied globally, reducing the complexity of control and interconnect resources. This simplification is achieved by shuttling...
| Main Authors: | , , , , , |
|---|---|
| פורמט: | Journal article |
| שפה: | English |
| יצא לאור: |
Springer Nature
2024
|