Efficient zero-knowledge arguments for arithmetic circuits in the discrete log setting
We provide a zero-knowledge argument for arithmetic circuit satisfiability with a communication complexity that grows logarithmically in the size of the circuit. The round complexity is also logarithmic and for an arithmetic circuit with fan-in 2 gates the computation of the prover and verifier is l...
| Main Authors: | , , , , |
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| Format: | Conference item |
| Published: |
Springer, Berlin, Heidelberg
2016
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