Area optimisation for field-programmable gate arrays in SystemC hardware compilation
This paper discusses a pair of synthesis algorithms that optimise a SystemC design to minimise area when targeting FPGAs. Each can significantly improve the synthesis of a high-level language construct, thus allowing a designer to concentrate more on an algorithm description and less on hardware-spe...
| Prif Awduron: | , , |
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| Fformat: | Journal article |
| Iaith: | English |
| Cyhoeddwyd: |
Hindawi Publishing Corporation
2008
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| Pynciau: |