Haller, L., & Singh, S. (2010). Relieving capacity limits on FPGA−based SAT−solvers.
Lua i Stíl Chicago (17ú heag.)Haller, L., agus S. Singh. Relieving Capacity Limits on FPGA−based SAT−solvers. 2010.
Lua MLA (9ú heag.)Haller, L., agus S. Singh. Relieving Capacity Limits on FPGA−based SAT−solvers. 2010.
Rabhadh: Seans nach mbeach na luanna seo go hiomlán cruinn i ngach uile chás.