Haller, L., & Singh, S. (2010). Relieving capacity limits on FPGA−based SAT−solvers.
Chicago Style (17th ed.) CitationHaller, L., and S. Singh. Relieving Capacity Limits on FPGA−based SAT−solvers. 2010.
MLA引文Haller, L., and S. Singh. Relieving Capacity Limits on FPGA−based SAT−solvers. 2010.
警告:這些引文格式不一定是100%准確.