Synthesising Optimal Timing Delays for Timed I/O Automata
In many real-time embedded systems, the choice of values for the timing delays can crucially a ect the safety or quantitative charac- teristics of their execution. We propose a parameter synthesis algorithm that nds optimal timing delays guaranteeing that the system satis es a given quantitative pro...
| Հիմնական հեղինակներ: | , , , |
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| Ձևաչափ: | Report |
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DCS
2014
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