Synthesising Optimal Timing Delays for Timed I/O Automata

Synthesising Optimal Timing Delays for Timed I/O Automata

In many real-time embedded systems, the choice of values for the timing delays can crucially a ect the safety or quantitative charac- teristics of their execution. We propose a parameter synthesis algorithm that nds optimal timing delays guaranteeing that the system satis es a given quantitative pro...

Disgrifiad llawn

Manylion Llyfryddiaeth
Prif Awduron:	Diciolla, M, Kim, C, Kwiatkowska, M, Mereacre, A
Fformat:	Report
Cyhoeddwyd:	DCS 2014

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