A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process
For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 μm2. Record NMOS/PMOS drive currents of 1000/575 μA/μm, respectively, have been achieved at 1 n...
| Main Authors: | , , , , , , , , , , , , , , , , , , , , , , , , |
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| Format: | Conference item |
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2008
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| _version_ | 1797079431577075712 |
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| author | Chen, X Samavedam, S Narayanan, V Stein, K Hobbs, C Baiocco, C Li, W Jaeger, D Zaleski, M Yang, H Kim, N Lee, Y Zhang, D Kang, L Chen, J Zhuang, H Sheikh, A Wallner, J Aquilino, M Han, J Jin, Z Li, J Massey, G Kalpat, S Jha, R |
| author_facet | Chen, X Samavedam, S Narayanan, V Stein, K Hobbs, C Baiocco, C Li, W Jaeger, D Zaleski, M Yang, H Kim, N Lee, Y Zhang, D Kang, L Chen, J Zhuang, H Sheikh, A Wallner, J Aquilino, M Han, J Jin, Z Li, J Massey, G Kalpat, S Jha, R |
| author_sort | Chen, X |
| collection | OXFORD |
| description | For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 μm2. Record NMOS/PMOS drive currents of 1000/575 μA/μm, respectively, have been achieved at 1 nA/μm off-current and 1.1V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L gate=30nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements. © 2008 IEEE. |
| first_indexed | 2024-03-07T00:45:45Z |
| format | Conference item |
| id | oxford-uuid:84956c72-067c-4e7b-b804-2fc1f81ce66b |
| institution | University of Oxford |
| last_indexed | 2024-03-07T00:45:45Z |
| publishDate | 2008 |
| record_format | dspace |
| spelling | oxford-uuid:84956c72-067c-4e7b-b804-2fc1f81ce66b2022-03-26T21:52:08ZA cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first processConference itemhttp://purl.org/coar/resource_type/c_5794uuid:84956c72-067c-4e7b-b804-2fc1f81ce66bSymplectic Elements at Oxford2008Chen, XSamavedam, SNarayanan, VStein, KHobbs, CBaiocco, CLi, WJaeger, DZaleski, MYang, HKim, NLee, YZhang, DKang, LChen, JZhuang, HSheikh, AWallner, JAquilino, MHan, JJin, ZLi, JMassey, GKalpat, SJha, RFor the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 μm2. Record NMOS/PMOS drive currents of 1000/575 μA/μm, respectively, have been achieved at 1 nA/μm off-current and 1.1V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L gate=30nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements. © 2008 IEEE. |
| spellingShingle | Chen, X Samavedam, S Narayanan, V Stein, K Hobbs, C Baiocco, C Li, W Jaeger, D Zaleski, M Yang, H Kim, N Lee, Y Zhang, D Kang, L Chen, J Zhuang, H Sheikh, A Wallner, J Aquilino, M Han, J Jin, Z Li, J Massey, G Kalpat, S Jha, R A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process |
| title | A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process |
| title_full | A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process |
| title_fullStr | A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process |
| title_full_unstemmed | A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process |
| title_short | A cost effective 32nm high-K/metal gate CMOS technology for low power applications with single-metal/gate-first process |
| title_sort | cost effective 32nm high k metal gate cmos technology for low power applications with single metal gate first process |
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