Formal Correctness of an Automotive Bus Controller Implementation at Gate−Lavel
We formalize the correctness of a real-time scheduler in a time-triggered architecture. Where previous research elaborated on real-time protocol correctness, we extend this work to gate-level hardware. This requires a sophisticated analysis of analog bit-level synchronization and message transmissio...
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Format: | Conference item |
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Springer Science and Business Media
2008
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