Formal Correctness of an Automotive Bus Controller Implementation at Gate−Lavel

Formal Correctness of an Automotive Bus Controller Implementation at Gate−Lavel

We formalize the correctness of a real-time scheduler in a time-triggered architecture. Where previous research elaborated on real-time protocol correctness, we extend this work to gate-level hardware. This requires a sophisticated analysis of analog bit-level synchronization and message transmissio...

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Bibliographic Details
Main Authors:	Alkassar, E, B"ohm, P, Knapp, S
Format:	Conference item
Published:	Springer Science and Business Media 2008

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