Loop tiling in large-scale stencil codes at run-time with OPS
The key common bottleneck in most stencil codes is data movement, and prior research has shown that improving data locality through optimisations that schedule across loops do particularly well. However, in many large PDE applications it is not possible to apply such optimisations through compilers...
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| Format: | Journal article |
| Published: |
Institute of Electrical and Electronics Engineers
2017
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