Quantum interference in silicon one-dimensional junctionless nanowire field-effect transistors

Quantum interference in silicon one-dimensional junctionless nanowire field-effect transistors

We investigate the low-temperature transport in 8-nm-diam Si junctionless nanowire field-effect transistors fabricated by top down techniques with a wraparound gate and two different phosphorus doping concentrations. First we extract the intrinsic gate capacitance of the device geometry from a devic...

Disgrifiad llawn

Manylion Llyfryddiaeth
Prif Awduron:	Schupp, F, Mirza, M, Maclaren, D, Briggs, G, Paul, D, Mol, J
Fformat:	Journal article
Iaith:	English
Cyhoeddwyd:	American Physical Society 2018

Eitemau Tebyg

One dimensional transport in silicon nanowire junction-less field effect transistors
gan: Mirza, M, et al.
Cyhoeddwyd: (2017)

One dimensional transport in silicon nanowire junction-less field effect transistors
gan: Muhammad M. Mirza, et al.
Cyhoeddwyd: (2017-06-01)

Junctionless Silicon Nanowire Resonator
gan: Sebastian T. Bartsch, et al.
Cyhoeddwyd: (2014-01-01)

Fabrication and simulation of lithographically defined junctionless lateral gate silicon nanowire transistors
gan: Larki, Farhad
Cyhoeddwyd: (2012)

In-situ doped junctionless polysilicon nanowires field effect transistors for low-cost biosensors
gan: Azeem Zulfiqar, et al.
Cyhoeddwyd: (2017-04-01)

Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures
gan: Thales Augusto Ribeiro, et al.
Cyhoeddwyd: (2021-01-01)

Fabrication and simulation of P-type junctionless silicon nanowire transistor using silicon on insulator and atomic force microscope nano lithography
gan: Dehzangi, Arash
Cyhoeddwyd: (2012)

Fabrication of p-type Double gate and Single gate Junctionless silicon nanowire transistor by Atomic force microscopy nanolithography
gan: Dehzangi, Arash, et al.
Cyhoeddwyd: (2013)

JUNCTIONLESS FIELD-EFFECT TRANSISTORS : Design, Modeling,and Simulation /
gan: Sahay, Shubham, author, et al.
Cyhoeddwyd: (2019)

Effect of traps and defects on high temperature performance of Ge channel junctionless nanowire transistors
gan: Chuanchuan Sun, et al.
Cyhoeddwyd: (2017-07-01)

Pinch-off effect in p-type double gate and single gate junctionless silicon nanowire transistor fabricated by atomic force microscopy nanolithography
gan: Larki, Farhad, et al.
Cyhoeddwyd: (2013)

Planar Junctionless Field-Effect Transistor for Detecting Biomolecular Interactions
gan: Rajendra P. Shukla, et al.
Cyhoeddwyd: (2022-08-01)

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates
gan: Tung-Yu Liu, et al.
Cyhoeddwyd: (2015-01-01)

A New Heterostructure Junctionless Tunnel Field Effect Transistor with Silicon-on-Nothing Technique for DC Parameter Improvement
gan: Amin Vanak, et al.
Cyhoeddwyd: (2024-04-01)

Performance evaluation of silicon-on-insulator junctionless transistor based 6T and 8T sram cells /
gan: Muhammad Faris Md. Noor, 1996-, author, et al.
Cyhoeddwyd: (2019)

Performance evaluation of silicon-on-insulator junctionless transistor based 6T and 8T sram cells /
gan: Muhammad Faris Md. Noor, 1996-, author, et al.
Cyhoeddwyd: (2019)

Impact of device parameter variation on the performance of n-type junctionless nanowire transistor with high-k dielectrics /
gan: Mohammed Adamu Sule, 1984-, author, et al.
Cyhoeddwyd: (2019)

Impact of device parameter variation on the performance of n-type junctionless nanowire transistor with high-k dielectrics /
gan: Mohammed Adamu Sule, 1984-, author, et al.
Cyhoeddwyd: (2019)

Optimization of 20nm junctionless nanowire transistor using Taguchi method for higher drive current with strained /
gan: Nurul Liyana Nasuha Omar, 1996-, author, et al.
Cyhoeddwyd: (2019)

Optimization of 20nm junctionless nanowire transistor using Taguchi method for higher drive current with strained /
gan: Nurul Liyana Nasuha Omar, 1996-, author, et al.
Cyhoeddwyd: (2019)

Sub-10-nm Asymmetric Junctionless Tunnel Field-Effect Transistors
gan: Chun-Hsing Shih, et al.
Cyhoeddwyd: (2014-01-01)

Performance Investigation of Single Grain Boundary Junctionless Field Effect Transistor
gan: Mamidala Saketh Ram, et al.
Cyhoeddwyd: (2016-01-01)

Piezoresistive sensing performance of junctionless nanowire FET
gan: Singh, Pushpapraj, et al.
Cyhoeddwyd: (2013)

A Silicon Nanowire Ferroelectric Field‐Effect Transistor
gan: Violetta Sessi, et al.
Cyhoeddwyd: (2020-04-01)

Interference-based molecular transistors
gan: Li, Y, et al.
Cyhoeddwyd: (2016)

Accuracy balancing for the simulation of gate-all-around junctionless nanowire transistors using discrete Wigner transport equation
gan: Kyoung-Youm Kim, et al.
Cyhoeddwyd: (2018-11-01)

Junctionless nanosheet gate‐all‐around transistors fabricated on void embedded silicon on insulator substrate
gan: Zhiqiang Mu, et al.
Cyhoeddwyd: (2023-02-01)

Characterization of silicon nanowire transistor
gan: Al Ariqi, Hani Taha, et al.
Cyhoeddwyd: (2019)

Back-gated Nb-doped MoS2 junctionless field-effect-transistors
gan: Gioele Mirabelli, et al.
Cyhoeddwyd: (2016-02-01)

Study of the side gate junctionless transistor in accumulation region
gan: Dehzangi, Arash, et al.
Cyhoeddwyd: (2016)

Simple estimation of intrinsic electrical parameters in junctionless transistors
gan: Dae-Young Jeon
Cyhoeddwyd: (2020-09-01)

Parameter variations of 20NM GAAS junctionless-gate-all-around field-effect transistor with quantum mechanical effects /
gan: Muhammad Faidzal Mohamad Rasol, 1996-, author 622246, et al.
Cyhoeddwyd: (2021)

Parameter variations of 20NM GAAS junctionless-gate-all-around field-effect transistor with quantum mechanical effects /
gan: Muhammad Faidzal Mohamad Rasol, 1996-, author 622246
Cyhoeddwyd: (2021)

Silicon nanowires, cryogenic control and radio-frequency read-out for quantum devices
gan: Schupp, F
Cyhoeddwyd: (2018)

Quantum interference enhances the performance of single-molecule transistors
gan: Chen, Z, et al.
Cyhoeddwyd: (2024)

Rational Design of a Planar Junctionless Field-Effect Transistor for Sensing Biomolecular Interactions
gan: Rajendra P. Shukla, et al.
Cyhoeddwyd: (2024-03-01)

Junctionless Poly-Si Nanowire FET With Gated Raised S/D
gan: Lun-Chun Chen, et al.
Cyhoeddwyd: (2016-01-01)

The feasibility of a quasi-one-dimensional (QDI) nanowire transistor /
gan: 273686 Lau, Hui Houg, et al.
Cyhoeddwyd: (2008)

Numerical investigation of channel width variation in junctionless transistors performance
gan: Dehzangi, Arash, et al.
Cyhoeddwyd: (2013)

Tri-gate junctionless transistors with electrostatically highly doped channel
gan: Dae-Young Jeon
Cyhoeddwyd: (2023-11-01)