Word level predicate abstraction and refinement for verifying RTL verilog

Word level predicate abstraction and refinement for verifying RTL verilog

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Model checking techniques applied to large industrial circuits suffer from the state space explosion problem. A major technique to address this problem is abstraction. The most commonly used abstraction technique for hardware verification is localization reduction, which removes latches that are not...

書誌詳細
主要な著者:	Jain, H, Sharygina, N, Kroening, D, Clarke, E
その他の著者:	Jr, W
フォーマット:	Conference item
出版事項:	Association for Computing Machinery 2005

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