Real-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC
Obtaining highly accurate depth from stereo images in real time has many applications across computer vision and robotics, but in some contexts, upper bounds on power consumption constrain the feasible hardware to embedded platforms such as FPGAs. Whilst various stereo algorithms have been deployed...
| Main Authors: | , , , , , , , |
|---|---|
| Format: | Journal article |
| Published: |
IEEE
2019
|
| _version_ | 1826296979804651520 |
|---|---|
| author | Rahnama, O Cavallari, T Golodetz, S Tonioni, A Joy, T Di Stefano, L Walker, S Torr, P |
| author_facet | Rahnama, O Cavallari, T Golodetz, S Tonioni, A Joy, T Di Stefano, L Walker, S Torr, P |
| author_sort | Rahnama, O |
| collection | OXFORD |
| description | Obtaining highly accurate depth from stereo images in real time has many applications across computer vision and robotics, but in some contexts, upper bounds on power consumption constrain the feasible hardware to embedded platforms such as FPGAs. Whilst various stereo algorithms have been deployed on these platforms, usually cut down to better match the embedded architecture, certain key parts of the more advanced algorithms, e.g., those that rely on unpredictable access to memory or are highly iterative in nature, are difficult to deploy efficiently on FPGAs, and thus the depth quality that can be achieved is limited. In this brief, we leverage an FPGA-CPU chip to propose a novel, sophisticated, stereo approach that combines the best features of semi-global matching and ELAS-based methods to compute highly accurate dense depth in real time. Our approach achieves an 8.7% error rate on the challenging KITTI 2015 dataset at over 50 frames/s, with a power consumption of only 5 W. |
| first_indexed | 2024-03-07T04:24:38Z |
| format | Journal article |
| id | oxford-uuid:cc337c7a-70ff-49f8-a9f9-5f43a34d9805 |
| institution | University of Oxford |
| last_indexed | 2024-03-07T04:24:38Z |
| publishDate | 2019 |
| publisher | IEEE |
| record_format | dspace |
| spelling | oxford-uuid:cc337c7a-70ff-49f8-a9f9-5f43a34d98052022-03-27T07:20:14ZReal-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoCJournal articlehttp://purl.org/coar/resource_type/c_dcae04bcuuid:cc337c7a-70ff-49f8-a9f9-5f43a34d9805Symplectic Elements at OxfordIEEE2019Rahnama, OCavallari, TGolodetz, STonioni, AJoy, TDi Stefano, LWalker, STorr, PObtaining highly accurate depth from stereo images in real time has many applications across computer vision and robotics, but in some contexts, upper bounds on power consumption constrain the feasible hardware to embedded platforms such as FPGAs. Whilst various stereo algorithms have been deployed on these platforms, usually cut down to better match the embedded architecture, certain key parts of the more advanced algorithms, e.g., those that rely on unpredictable access to memory or are highly iterative in nature, are difficult to deploy efficiently on FPGAs, and thus the depth quality that can be achieved is limited. In this brief, we leverage an FPGA-CPU chip to propose a novel, sophisticated, stereo approach that combines the best features of semi-global matching and ELAS-based methods to compute highly accurate dense depth in real time. Our approach achieves an 8.7% error rate on the challenging KITTI 2015 dataset at over 50 frames/s, with a power consumption of only 5 W. |
| spellingShingle | Rahnama, O Cavallari, T Golodetz, S Tonioni, A Joy, T Di Stefano, L Walker, S Torr, P Real-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC |
| title | Real-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC |
| title_full | Real-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC |
| title_fullStr | Real-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC |
| title_full_unstemmed | Real-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC |
| title_short | Real-time highly accurate dense depth on a power budget using an FPGA-CPU hybrid SoC |
| title_sort | real time highly accurate dense depth on a power budget using an fpga cpu hybrid soc |
| work_keys_str_mv | AT rahnamao realtimehighlyaccuratedensedepthonapowerbudgetusinganfpgacpuhybridsoc AT cavallarit realtimehighlyaccuratedensedepthonapowerbudgetusinganfpgacpuhybridsoc AT golodetzs realtimehighlyaccuratedensedepthonapowerbudgetusinganfpgacpuhybridsoc AT tonionia realtimehighlyaccuratedensedepthonapowerbudgetusinganfpgacpuhybridsoc AT joyt realtimehighlyaccuratedensedepthonapowerbudgetusinganfpgacpuhybridsoc AT distefanol realtimehighlyaccuratedensedepthonapowerbudgetusinganfpgacpuhybridsoc AT walkers realtimehighlyaccuratedensedepthonapowerbudgetusinganfpgacpuhybridsoc AT torrp realtimehighlyaccuratedensedepthonapowerbudgetusinganfpgacpuhybridsoc |