The impact of hardware scheduling mechanisms on the performance and cost of processor designs
Hardware schedulers supporting out-of-order execution are widespread nowadays. Nevertheless, studies quantifying the impact of schedulers on the performance and cost of processors are rare. The paper tries to close this gap. It turns out that the hardware schedulers can double the performance at a m...
Autors principals: | Müller, S, Leister, H, Dell, P, Gerteis, N, Kroening, D |
---|---|
Altres autors: | Cap, C |
Format: | Conference item |
Publicat: |
dblp computer science bibliography
1999
|
Ítems similars
-
The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs.
per: Mueller, S, et al.
Publicat: (1999) -
Dedicated digital processors : methods in hardware/software system design /
per: 276644 Mayer-Lindenberg, F.
Publicat: (2004) -
A Hardware Assembler for 8080 Processor
per: D. I. Cowie
Publicat: (1978-04-01) -
Exploring Optimal Cost-Performance Designs for RAW processors
per: Moritz, Csaba Andras, et al.
Publicat: (2023) -
APRON: A Cellular Processor Array Simulation and Hardware Design Tool
per: David R. W. Barr, et al.
Publicat: (2009-01-01)