The impact of hardware scheduling mechanisms on the performance and cost of processor designs

The impact of hardware scheduling mechanisms on the performance and cost of processor designs

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Hardware schedulers supporting out-of-order execution are widespread nowadays. Nevertheless, studies quantifying the impact of schedulers on the performance and cost of processors are rare. The paper tries to close this gap. It turns out that the hardware schedulers can double the performance at a m...

Disgrifiad llawn

Manylion Llyfryddiaeth
Prif Awduron:	Müller, S, Leister, H, Dell, P, Gerteis, N, Kroening, D
Awduron Eraill:	Cap, C
Fformat:	Conference item
Cyhoeddwyd:	dblp computer science bibliography 1999

Eitemau Tebyg

The Impact of Hardware Scheduling Mechanisms on the Performance and Cost of Processor Designs.
gan: Mueller, S, et al.
Cyhoeddwyd: (1999)

Dedicated digital processors : methods in hardware/software system design /
gan: 276644 Mayer-Lindenberg, F.
Cyhoeddwyd: (2004)

A Hardware Assembler for 8080 Processor
gan: D. I. Cowie
Cyhoeddwyd: (1978-04-01)

Exploring Optimal Cost-Performance Designs for RAW processors
gan: Moritz, Csaba Andras, et al.
Cyhoeddwyd: (2023)

APRON: A Cellular Processor Array Simulation and Hardware Design Tool
gan: David R. W. Barr, et al.
Cyhoeddwyd: (2009-01-01)

Tao--an architecturally balanced reconfigurable hardware processor
gan: Huang, Andrew S. (Andrew Shane)
Cyhoeddwyd: (2005)

Thread Scheduling Mechanisms for Multiple-Context Parallel Processors
gan: Fiske, James A. Stuart
Cyhoeddwyd: (2004)

Thread scheduling mechanisms for multiple-context parallel processors
gan: Fiske, James Alexander Stuart
Cyhoeddwyd: (2007)

Scheduling jobs on multi-processors
gan: Neetika, Bansal
Cyhoeddwyd: (2012)

OKI advanced array processor (AAP) hardware description
Cyhoeddwyd: (2004)

Digital neural processor hardware implementation for character recognition /
gan: 424809 Kumaara Velan Munusamy
Cyhoeddwyd: (2000)

The 80386, 80486 and pentium processor : hardware, software and interfacing /
gan: 391611 Triebel, Walter A.
Cyhoeddwyd: (1998)

Algorithms for Scheduling Tasks on Unrelated Processors
gan: Davis, Ernest, et al.
Cyhoeddwyd: (2023)

Optimal scheduling for two-processor systems /
gan: Coffman, E. G. (Edward Grady), 1934-, et al.

Task scheduling in parallel processor systems /
gan: 443850 Syarifah Zyurina Nordin
Cyhoeddwyd: (2011)

Static Scheduling of Periodic Hardware Tasks with Precedence and Deadline Constraints on Reconfigurable Hardware Devices
gan: Ikbel Belaid, et al.
Cyhoeddwyd: (2011-01-01)

Scheduling Algorithm: Tasks Scheduling Algorithm for Multiple Processors with Dynamic Reassignment
gan: Pradeep Kumar Yadav, et al.
Cyhoeddwyd: (2008-01-01)

Power Saving for Hardware Accelerated Applications With Dynamical Processor Switching
gan: Ko Natori, et al.
Cyhoeddwyd: (2024-01-01)

Scheduling for hardware/software partitioning in embedded system design
gan: Engels, Daniel Wayne, 1970-
Cyhoeddwyd: (2014)

Register transfer level design of compression processor core using verilog hardware description language /
gan: Roslee Mohd. Sabri, 1978-, et al.
Cyhoeddwyd: (2007)

Co-design of Compiler and Hardware Techniques to Reduce Program Code Size on a VLIW Processor
gan: Eric J. Stotzer, et al.
Cyhoeddwyd: (2012-08-01)

Modelling and developing co-scheduling strategies on multicore processors
gan: Zhu, H, et al.
Cyhoeddwyd: (2015)

Median filter using altera nios II processor and sort hardware /
gan: 267473 Nadiah Azmi, et al.
Cyhoeddwyd: (2008)

Median filter using nios II processor with sort hardware accelerator /
gan: Chen, Kah Yee, 198- , author, et al.
Cyhoeddwyd: (2009)

Accelerating Population Count with a Hardware Co-Processor for MicroBlaze
gan: Iouliia Skliarova
Cyhoeddwyd: (2021-04-01)

Hardware Implementation of Residue Multipliers based Signed RNS Processor for Cryptosystems
gan: E. Sekar, et al.
Cyhoeddwyd: (2020-09-01)

Modern processor design : fundamentals of superscalar processors /
gan: 204626 Shen, John Paul, et al.
Cyhoeddwyd: (2005)

Modern processor design : fundamentals of superscalar processors /
gan: 204626 Shen, John Paul, et al.
Cyhoeddwyd: (2003)

Three Processor Allocation Approaches towards EDF Scheduling for Performance Asymmetric Multiprocessors
gan: Peng Wu, et al.
Cyhoeddwyd: (2023-04-01)

Automatic analysis of scratch-pad memory code for heterogeneous multicore processors
gan: Donaldson, A, et al.
Cyhoeddwyd: (2010)

Proving the Correctness of Processors with Delayed Branch using Delayed PC
gan: Mueller, S, et al.
Cyhoeddwyd: (2000)

Performance Characterization of Hardware/Software Communication Interfaces in End-to-End Power Management Solutions of High-Performance Computing Processors
gan: Antonio del Vecchio, et al.
Cyhoeddwyd: (2024-11-01)

SCHEDULING PROBLEMS OF STATIONARY OBJECTS WITH THE PROCESSOR IN ONE-DIMENSIONAL ZONE
gan: N. A. Dunichkina, et al.
Cyhoeddwyd: (2015-06-01)

Formal techniques for effective co-verification of hardware/software co-designs
gan: Mukherjee, R, et al.
Cyhoeddwyd: (2017)

A Self-Checking Hardware Journal for a Fault-Tolerant Processor Architecture
gan: Mohsin Amin, et al.
Cyhoeddwyd: (2011-01-01)

Hardware-Based Implementation of Algorithms for Data Replacement in Cache Memory of Processor Cores
gan: Larysa Titarenko, et al.
Cyhoeddwyd: (2024-07-01)

Gradient-descent hardware-aware training and deployment for mixed-signal neuromorphic processors
gan: Ugurcan Cakal, et al.
Cyhoeddwyd: (2024-01-01)

Hardware Prototyping and Validation of a W-ΔDOR Digital Signal Processor
gan: Gian Carlo Cardarilli, et al.
Cyhoeddwyd: (2019-07-01)

Efficient Hardware Implementation of Large Field-Size Elliptic Curve Cryptographic Processor
gan: Chiou-Yng Lee, et al.
Cyhoeddwyd: (2022-01-01)

Scheduling of Batch Processors in Semiconductor Manufacturing – A Review
gan: Mathirajan, M., et al.
Cyhoeddwyd: (2003)