Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog

Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog

As a first step, most model checkers used in the hardware industry convert a high-level register-transfer-level (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels and, thus, are less scalable. The RT...

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Autors principals:	Jain, H, Kroening, D, Sharygina, N, al., E
Format:	Journal article
Publicat:	Institute of Electrical and Electronics Engineers 2008

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