Word-level predicate-abstraction and refinement rechniques for verifying RTL Verilog
As a first step, most model checkers used in the hardware industry convert a high-level register-transfer-level (RTL) design into a netlist. However, algorithms that operate at the netlist level are unable to exploit the structure of the higher abstraction levels and, thus, are less scalable. The RT...
| 主要な著者: | , , , |
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| フォーマット: | Journal article |
| 出版事項: |
Institute of Electrical and Electronics Engineers
2008
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